Typically, CIS devices are mounted in mobile phone cameras, digital cameras, etc, and include an array of active pixel sensors and driving circuitry for electronically capturing images, converting the images into electrical signals, and transmitting the electrical signals to a display driver. Typically, the driving circuitry comprises a ramp comparison type column ADC circuit structure. FIG. 1 is a block diagram illustrating a CIS device (10) having a well-known architecture comprising a pixel array (11), a ramp signal generator (12), a plurality of comparators (13), a counter (14) and a plurality of latches (15).
As is known in the art, the pixel array (11) captures an image. The comparators (13), which are employed in CDS circuits, receive analog signals output from the pixel array (11) and compare the analog signals to a ramp signal VRAMP (which is incremented with a predetermined slope) output from the ramp signal generator (12) to digitize the analog signals. The comparators (13) output digital values having a logic high state or a logic low state at timings that are different from each other. When the comparators (13) output digital values at timings that are different from each other, the counter (14) outputs counter values corresponding to timings at which the digital values are varied. The latches (15) store and output digital signals (D1, D2, . . . , DN), which are proportional to the analog signals output from the pixel array (11). The output digital signals (D1, D2, . . . , DN) are processed and input to a predetermined display device to display the photographed image.
In the conventional CIS device (10) of FIG. 1, a ramp comparison type column ADC employs as many comparators as there are columns in the pixel array (11). For example, in the CIS pixel array (11) having 380,000 pixels, the total number of effective columns amounts to about 640. To compare the ramp signal VRAMP with the analog signals output from the pixel array (11) and generate digital signals, the comparators (13) use a conventional inverter circuit (30), such as depicted in FIG. 14, consisting of one PMOSFET (p-type metal oxide semiconductor field effect transistor) (M1) and one NMOSFET (n-type metal oxide semiconductor field effect transistor) (M2), connected in series between VDD and VSS source voltages.
With the conventional inverter (30) architecture, an instantaneous transition current (a peak current) is generated at an input voltage VIN between a first logic state “0” and a second logic state “1”, that is, a logic threshold voltage (for example, ½ of VDD), which disadvantageously results in a significant consumption of power. Indeed, assuming a light signal of the same high intensity is applied to all 380,000 pixels in the pixel array (11) of the CIS device (10) of FIG. 1 and signal conversions are simultaneously performed in all of about 640 columns, the instantaneous current at the logic threshold voltage would reach several hundreds mA. The generation of such a large current results in a large power consumption and the current spike influences power supply lines connected to the entire circuit producing noise components in output images or other circuit elements, thereby causing erroneous operation.